1. Field
The present invention relates to electrostatic discharge (ESD) protection schemes for microelectronics and, more specifically, to biased ESD protection schemes for microelectronics.
2. Background Information
Advancements in silicon processing technologies employed to manufacture microelectronics, such as integrated circuits (ICs), may include reduction in circuit element sizes. Such reduction in circuit element sizes, which may be referred to as xe2x80x9cscalingxe2x80x9d, is one way the performance of microelectronic devices manufactured employing such processes may be improved. Current processing technologies have circuit element dimensions, such as transistor sizes, which are smaller than 200 nanometers (nm). Such processes are typically referred to as xe2x80x9cdeep sub-micronxe2x80x9d processes.
However, such scaling may also result in undesired effects. For example, as circuit element sizes are reduced, or xe2x80x9cscaledxe2x80x9d, such circuit elements may become more susceptible to damage from electrostatic discharge (ESD) events due, at least in part, to thinner oxides and/or shallower junctions typically associated with such scaled circuit elements. An ESD event may occur, for example, when an electrically charged body comes in contact with, or in close proximity to a microelectronic device. Alternatively, an ESD event may occur when an electric charge accumulates on a microelectronic device and that microelectronic device then comes in contact with, or in close proximity to a grounded body. Of course, other situations also exist that may result in an ESD event.
Experimentation has shown that p-channel devices embodied on microelectronic components manufactured using advanced microelectronic manufacturing processes may be particularly susceptible to damage from certain types of ESD events, as compared with prior manufacturing processes. This susceptibility may be due, at least in part, to scaling in such processes and, therefore, may be exacerbated by further scaling on future manufacturing processes. Additionally, scaling may result in n-channel devices becoming more susceptible to ESD damage from snap-back events, such as those leading to secondary breakdown. Therefore, based on the foregoing, alternative schemes for ESD protection are desirable.